The use of bi-directional shift register stages for drive circuits in liquid crystal displays (LCD) to allow a forward or a reverse display image. By causing the image to be scanned in one direction a forward, normal or non-reverse image may be displayed. However, when the image is scanned in a second direction, a reversed image may be displayed. U.S. Pat. No. 5,894,296, entitled “Bidirectional Signal Transmission Network and Bidirectional Signal Transfer Shift Register,” issued Apr. 13, 1999, to Maekawa, teaches the use of bidirectional shift register control circuits in the LCD displays. In this circuit, the input and output terminals of the shift register are connected in a manner to construct a multi-stage structure, having a forward route gate element interposed in a connection between the output terminals.
FIG. 1a illustrates an exemplary conventional bi-directional shift register and control circuit. In this illustrative example, three shift register stages, represented as 110, 120, and 130, are shown serially connected through control circuits 115, 125, and 135, respectively. Shift registers stages 110, 120 and 130 conventionally are referred to, and referred to herein, as the (N−1), (N) and (N+1) stages of shift register circuit 100. This generalization of shift register 100 into (N−1), (N) and (N+1) elements is terminology recognized by those skilled in the art in that the operation of shift registers is performed with regard to adjacent register elements. The generalization of shift register 100 is further appropriate as it would be understood that any number of registers may be electrically connected, physically or logically, to create a shifting device of any size.
Each register further includes an input terminal and an output terminal. Input terminals for the three illustrated register stages are denoted as 112, 122, and 132, respectively, while the output terminals are denoted as 114, 124, and 134, respectively. Control circuits 115, 125 and 135 are electrically connected to an input terminal of a corresponding register stage, whereas the output terminal of each of the register stages is electrically connected to an adjacent bi-directional control circuit. Hence, the output terminal 124 of register stage 120 provides an input to control circuits 115 and 135, while output terminals 114 and 134 of shift registers 110 and 130, respectively, provide input to control circuit 125 and not shown adjacent register stages.
Control lines CL1 145 and CL2 140 are used to set control circuits 115, 125, and 135 in a manner to direct the data in the shift register to be shifted in a forward or reverse direction. Typically control lines CL1 145 and CL2 140 are set to different values. When CL1 145 is set to a high level, CL2 140 is set to a low level to operate in a first direction and reversed operate in second direction.
FIGS. 1b and 1c illustrate forward and reverse timing sequences of the shift register 100 shown in FIG. 1a. Referring to FIG. 1a, a pulse 116p output on output terminal 114 is provided as an input to control circuit 125, which is further provided to input terminal 122 of shift register stage 120. Shift register stage 120 then provides pulse 126p from output terminal 124 to input of control circuit 135. Control circuit 135 provides an input voltage to shift register 130 through input terminal 132. Shift register 130 then provides pulse 136p at output terminal 134. This progressive shifting of an initial pulse in a forward, i.e., “p,” direction continues for each of the stages in the shift register device. FIG. 1c illustrates a pulse shifting sequence in a reverse, i.e., “r,” direction for the shift register shown in FIG. 1a. In this case, pulse 136r on output terminal 134 is input to control circuit 125, which then provides an input to shift register stage 120. Shift register stage 120 generates pulse 126r on corresponding output line 124 that is applied as an input to control circuit 115. The process is repeated for each shift register stage in the shifting device.
FIG. 2 illustrates a conventional control circuit representative of an Nth register stage, for example, control circuit 125 and shift register stage 120. Within control circuit 125 are switches 210 and 220 that are operable to direct either the output of the N−1 stage, i.e., 116p, or the (N+1) stage, i.e., 136r, to input 122 of shift register stage 120. In this illustrated case, switches 210 and 220 are represented as n-type Field Effect Transistors (FETs). Control lines 140 and 145 are electrically connected to switches 220 and 210, respectively. In this case, when a high signal, e.g., Vdd, is applied to control line 145 and a low signal, e.g., Vss, is applied to control line 140, switch 210 is closed and switch 220 remains open. An input from an (N−1) stage, e.g., pulse 116p, is provided to the input of shift register stage 120 and data is shifted from the (N−1) stage to an Nth stage. Alternatively, when a high signal is applied to control line 140 and a low signal is applied to control line 145, switch 210 remains open and switch 220 is closed. In this case, an input from the (N+1) stage, e.g., 136r, is provided to the input of shift register stage 120 and data is reverse shifted from the (N+1) stage to an Nth stage.
A problem with the conventional implementation is that it may suffer from a gate element leakage. For example, if gate element 220 has a sufficient voltage leakage between its source and drain terminals, i.e., it cannot be sufficiently turned off by the control signal on CL2, that under positive forward shifting operation with CL2 at low level, for example, the pulsed signal voltage ‘(N+1) out’ may leak into the input terminal 122 of the electrically adjacent Nth shift register stage and introduce an error.
Hence, a shift register control circuit that allows for a complete turnoff of the non-conducting transistors is desirable.